|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or other- wise under any patent or patent rights of analog devices. t rademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t el: 781/329-4700 www.analog.com fa x: 781/326-8703 ? 2002 analog devices, inc. all rights reserved. ADUC836 microconverter ? , dual 16-bit - adcs with embedded 62 kb flash mcu features high resolution - adcs 2 independent adcs (16-bit resolution) 16-bit no missing codes, primary adc 16-bit rms (16-bit p-p) effective resolution @ 20 hz offset drift 10 nv/ c, gain drift 0.5 ppm/ c memory 62 kbytes on-chip flash/ee program memory 4 kbytes on-chip flash/ee data memory flash/ee, 100 year retention, 100 kcycles endurance 3 levels of flash/ee program memory security in-circuit serial download (no external hardware) high speed user download (5 seconds) 2304 bytes on-chip data ram 8051 based core 8051 compatible instruction set 32 khz external crystal on-chip programmable pll (12.58 mhz max) 3 16-bit timer/counter 26 programmable i/o lines 11 interrupt sources, 2 priority levels dual data pointer, extended 11-bit stack pointer on-chip peripherals internal power on reset circuit 12-bit voltage output dac dual 16-bit - dacs/pwms on-chip temperature sensor dual excitation current sources time interval counter (wake-up/rtc timer) uart, spi ? , a nd i 2 c ? serial i/o high speed baud rate generator (including 115,200) wa tchdog timer (wdt) po we r supply monitor (psm) power normal: 2.3 ma max @ 3.6 v (core clk = 1.57 mhz) power-down: 20 a max with wake-up timer running speci? ed for 3 v and 5 v operation pa ck age and temperature range 52-lead mqfp (14 mm 14 mm), ?40 c to +125 c 56-lead csp (8 mm 8 mm), ?40 c to +85 c applications intelligent sensors wei gh scales po rt able instrumentation, battery-powered systems 4?20 ma transmitters da ta logging precision system monitoring functional block diagram 62 kbytes flash/ee program memory 4 kbytes flash/ee data memory 2304 bytes user ram 3 16 bit timers baud r ate timer 4 parallel ports 8051-based mcu with additional peripherals power supply mon watchdog timer uart, spi, and i 2 c serial i/o ADUC836 xtal2 xtal1 buf agnd refin+ refin internal band gap v ref ain1 ain2 ain3 ain4 ain5 auxiliary 16-bit - adc primary 16-bit - adc mux osc av dd mux pga dual 16-bit - dac buf dac current source av dd iexc1 iexc2 pwm0 pwm1 dual 16-bit pwm w ake- up/ rtc timer temp sensor external v ref detect 12-bit dac mux dgnd dv dd reset por pll and prog clock div general description the ADUC836 is a complete smart transducer front end, integrating two high resolution - adcs, an 8-bit mcu, and p rogram/data flash/ee memory on a single chip. the two independent adcs (primary and auxiliary) include a temperature sensor and a pga (allowing direct measurement of low level signals). the adcs with on-chip digital ltering and programmable output data rates are intended for the measure- ment of wide dynamic range, low frequency signals, such as those in weigh scale, strain gage, pressure transducer, or temperature measurement applications. the device operates from a 32 khz crystal with an on-chip pll generating a high frequency clock of 12.58 mhz. this clock is routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the microcontroller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle. 62 kbytes of nonvolatile flash/ee program memory, 4 kbytes of nonvolatile flash/ee data memory, and 2304 bytes of data ram are provided on-chip. the program memory can be con gured as data memory to give up to 60 kbytes of nv data memory in data logging applications. on-chip factory rm w are supports in-circuit serial download and debug modes (via uart), as well as single-pin emulation mode via the ea pin. the ADUC836 is supported by a quickstart development system featuring low cost software and hardware development tools. rev. 0
ADUC836 ?2? t able of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 functional block diagram . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . .1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 absolute maximum ratings . . . . . . . . . . . . . . . . .9 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . .9 detailed block diagram . . . . . . . . . . . . . . . . . . . .10 pin function descriptions . . . . . . . . . . . . . . . . . .10 memory organization . . . . . . . . . . . . . . . . . . . . . . .13 special function registers (sfrs) . . . . . . . . . .14 accumulator sfr (acc) . . . . . . . . . . . . . . . . . . . . . . . . . .14 b sfr (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 data pointer (dptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 stack pointer (sp and sph) . . . . . . . . . . . . . . . . . . . . . . . .15 program status word (psw) . . . . . . . . . . . . . . . . . . . . . . . .15 po w er control sfr (pcon) . . . . . . . . . . . . . . . . . . . . . . .15 ADUC836 con guration sfr (cfg836) . . . . . . . . . . . . . .15 complete sfr map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 adc sfr interface adcstat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 adcmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 adc0con . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 adc1con . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 adc0h/adc0m/adc1h/adc1l . . . . . . . . . . . . . . . . . .20 of0h/of0m/of1h/of1l . . . . . . . . . . . . . . . . . . . . . . . .20 gn0h/gn0m/gn1h/gn1l . . . . . . . . . . . . . . . . . . . . . . .20 sf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 icon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 primary and auxiliary adc noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 primary and auxiliary adc circuit description overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 primary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auxiliary adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 analog input channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 primary and auxiliary adc inputs . . . . . . . . . . . . . . . . . . .25 analog input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 programmable gain ampli er . . . . . . . . . . . . . . . . . . . . . . .25 bipolar/unipolar inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 burnout currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 excitation currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 reference detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 - modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 adc chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 nonvolatile flash/ee memory flash/ee memory overview . . . . . . . . . . . . . . . . . . . . . . . .29 flash/ee memory and the ADUC836 . . . . . . . . . . . . . . . . .29 ADUC836 flash/ee memory reliability . . . . . . . . . . . . . . .29 flash/ee program memory . . . . . . . . . . . . . . . . . . . . . . . .30 serial downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 parallel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 user download mode (uload) . . . . . . . . . . . . . . . . . . . .31 flash/ee program memory security . . . . . . . . . . . . . . . . . .31 lock, secure, and serial safe modes . . . . . . . . . . . . . . . . . .31 using the flash/ee data memory . . . . . . . . . . . . . . . . . . .32 econ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 programming the flash/ee data memory . . . . . . . . . . . . .33 flash/ee memory timing . . . . . . . . . . . . . . . . . . . . . . . . . .33 o ther on-chip peripherals dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 on-chip pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 time interval counter (wake-up/rtc timer) . . . . . . . . .40 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 po w er supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . .44 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 dual data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 8052 compatible on-chip peripherals parallel i/o ports 0? . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 ua rt operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . .57 baud rate generation using timer 1 and timer 2 . . . . . . .59 baud rate generation using timer 3 . . . . . . . . . . . . . . . . .60 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 hardware design considerations external memory interface . . . . . . . . . . . . . . . . . . . . . . . . .63 po w er supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 power-on reset (por) operation . . . . . . . . . . . . . . . . . . .64 po w er consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 wake-up from power-down latency . . . . . . . . . . . . . . . . .65 grounding and board layout recommendations . . . . . . . .66 ADUC836 system self-identi cation . . . . . . . . . . . . . . . . . .66 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 o ther hardware considerations in-circuit serial download access . . . . . . . . . . . . . . . . . . .67 embedded serial port debugger . . . . . . . . . . . . . . . . . . . . .67 single-pin emulation mode . . . . . . . . . . . . . . . . . . . . . . . .67 typical system con guration . . . . . . . . . . . . . . . . . . . . . . .68 q uickstart development system . . . . . . . . . . .69 timing specifications . . . . . . . . . . . . . . . . . . . . . . .70 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . .80 rev. 0 ADUC836 ?3? (av dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v, refin(+) = 2.5 v; refin(?) = agnd; agnd = dgnd = 0 v; xtal1/xtal2 = 32.768 khz crystal; all spec i ? ca tions t min to t max , unless oth er wise not ed.) p arameter ADUC836 test conditions/comments unit adc specifications conversion rate 5.4 on both channels hz mi n 105 programmable in 0.732 ms increments hz max primary adc no missing codes 2 16 20 hz update rate bits min resolution 13.5 range = ?0 mv, 20 hz update rate bits p-p typ 16 range = ?.56 v, 20 hz update rate bits p-p t yp output noise see tables x and xi in output noise varies with selected ADUC836 adc description update rate and gain range integral nonlinearity ?5 1 lsb ppm of fsr max offset error 3 ? v typ offset error drift ?0 nv/? typ full-scale error 4 ?0 range = ?0 mv to ?40 mv v typ ?.5 range = ?.28 v to ?.56 v l sb typ gain error drift 5 ?.5 ppm/? typ adc range matching ? ain = 18 mv v typ power supply rejection (psr) 95 ain = 7.8 mv, range = ?0 mv dbs typ 80 ain = 1 v, range = ?.56 v dbs typ common-mode dc rejection on ain 95 at dc, ain = 7.8 mv, range = ?0 mv dbs typ 113 at dc, ain = 1 v, range = ?.56 v dbs typ on refin 125 at dc, ain = 1 v, range = ?.56 v dbs typ common-mode 50 hz/60 hz rejection 20 hz up date rate on ain 95 50 hz/60 hz ? hz, ain = 7.8 mv, dbs typ range = ?0 mv 90 50 hz/60 hz ? hz, ain = 1 v, dbs ty p range = ?.56 v on refin 90 50 hz/60 hz ? hz, ain = 1 v, dbs typ range = ?.56 v normal mode 50 hz/60 hz rejection on ain 60 50 hz/60 hz ? hz, 20 hz update rate dbs typ on refin 60 50 hz/60 hz ? hz, 20 hz update rate dbs typ auxiliary adc no missing codes 2 16 bits min resolution 16 range = ?.5 v, 20 hz update rate bits p-p typ output noise see table xii in ADUC836 output noise varies with selected adc description update rate integral nonlinearity ?5 ppm of fsr max offset error 3 ? lsb typ offset error drift 1 v/? typ full-scale error 6 ?.5 lsb typ gain error drift 5 ?.5 ppm/? typ power supply rejection (psr) 80 ain = 1 v, 20 hz update rate dbs typ normal mode 50 hz/60 hz rejection on ain 60 50 hz/60 hz ? hz dbs t yp on refin 60 50 hz/60 hz ? hz, 20 hz update rate dbs typ da c performance dc speci cations 7 resolution 12 bits relative accuracy ? lsb typ differential nonlinearity ? guaranteed 12-bit monotonic lsb max offset error ?0 mv max gain error 8 ? av dd range % max ? v ref range % typ ac speci cations 2, 7 voltage output settling time 15 settling time to 1 lsb of final value s typ digital-to-analog glitch energy 10 1 lsb change at major carry nvs typ specifications 1 rev. 0 ?4? ADUC836 p arameter ADUC836 test conditions/comments unit internal reference adc reference reference voltage 1.25 ?1% initial tolerance @ 25?, v dd = 5 v v min/max power supply rejection 45 dbs typ reference tempco 100 ppm/? typ dac reference reference voltage 2.5 ?1% initial tolerance @ 25?, v dd = 5 v v min/max power supply rejection 50 dbs typ reference tempco ?00 ppm/? typ analog inputs/reference inputs primary adc differential input voltage ranges 9, 10 external reference voltage = 2.5 v rn2, rn1, rn0 of adc0con set to bipolar mode (adc0con3 = 0) ?0 0 0 0 (unipolar mode 0 mv to 20 mv) mv ?0 0 0 1 (unipolar mode 0 mv to 40 mv) mv ?0 0 1 0 (unipolar mode 0 mv to 80 mv) mv ?60 0 1 1 (unipolar mode 0 mv to 160 mv) mv ?20 1 0 0 (unipolar mode 0 mv to 320 mv) mv ?40 1 0 1 (unipolar mode 0 mv to 640 mv) mv ?.28 1 1 0 (unipolar mode 0 v to 1.28 v) v ?.56 1 1 1 (unipolar mode 0 v to 2.56 v) v analog input current 2 ? t max = 85? na max ? t max = 125? na max analog input current drift ? t max = 85? pa/? typ ?5 t max = 125? pa/? typ absolute ain voltage limits 2 agnd + 100 mv v min av dd ?100 mv v max auxiliary adc input voltage range 9, 10 0 to v ref unipolar mode, for bipolar mode v see note 11 average analog input current 125 input current will vary with input na/v typ average analog input current drift 2 ? voltage on the unbuffered auxiliary adc pa/v/? typ absolute ain voltage limits 2, 11 agnd ?30 mv v min av dd + 30 mv v max external reference inputs refin(+) to refin(? range 2 1 v min av dd v max average reference input current 1 both adcs enabled a/v typ average reference input current drift ?.1 na/ v/? typ ?o ext. ref trigger voltage 0.3 noxref bit active if v ref < 0.3 v v min 0.65 noxref bit inactive if v ref > 0.65 v v max adc system calibration full-scale calibration limit 1.05 fs v max zero-scale calibration limit ?.05 fs v min input span 0.8 fs v min 2.1 fs v max analog (dac) output voltage range 0 to v ref da crn = 0 in daccon sfr v typ 0 to av dd da crn = 1 in daccon sfr v typ resistive load 10 from dac output to agnd k typ capacitive load 100 from dac output to agnd pf typ output impedance 0.5 typ i sink 50 a typ temperature sensor accuracy ? ? typ thermal impedance ( ja ) 90 mqfp package ?/w typ 52 csp package (base floating) 12 ?/w typ specifications (continued) rev. 0 ADUC836 ?5? p arameter ADUC836 test conditions/comments unit transducer burnout current sources ain+ current ?00 ain+ is the selected positive input na typ to the primary adc ain?current +100 ain?is the selected negative input na typ to the auxiliary adc initial tolerance @ 25? ?0 % typ drift 0.03 %/? typ excitation current sources output current ?00 available from each current source a typ initial tolerance @ 25? ?0 % typ drift 200 ppm/? typ initial current matching @ 25? ? matching between both current sources % typ drift matching 20 ppm/? typ line regulation (av dd ) 1 av dd = 5 v + 5% a/v typ load regulation 0.1 a/v typ output compliance 2 av dd ?0.6 v max agnd v min logic inputs all inputs except sclock, reset, and xtal1 2 v inl , input low voltage 0.8 dv dd = 5 v v max 0.4 dv dd = 3 v v max v inh , input high voltage 2.0 v min sclock and reset only (schmitt-triggered inputs) 2 v t+ 1.3/3 dv dd = 5 v v min/v max 0.95/2.5 dv dd = 3 v v min/v max v t 0.8/1.4 dv dd = 5 v v min/v max 0.4/1.1 dv dd = 3 v v min/v max v t+ ? v t 0.3/0.85 dv dd = 5 v v min/v max 0.3/0.85 dv dd = 3 v v min/v max input currents port 0, p1.2?1.7, ea ?0 v in = 0 v or v dd a max sclock, mosi, miso, ss 13 ?0 min, ?0 max v in = 0 v, dv dd = 5 v, internal pull-up a min/ a max ?0 v in = v dd , dv dd = 5 v a max reset ?0 v in = 0 v, dv dd = 5 v a max 35 min, 105 max v in = v dd , dv dd = 5 v, a min/ a max internal pull-down p1.0, p1.1, ports 2 and 3 ?0 v in = v dd , dv dd = 5 v a max ?80 v in = 2 v, dv dd = 5 v a min ?60 a max ?0 v in = 450 mv, dv dd = 5 v a min ?5 a max input capacitance 5 all digital inputs pf t yp crystal oscillator (xtal1 and xtal2) logic inputs, xtal1 only 2 v inl , input low voltage 0.8 dv dd = 5 v v max 0.4 dv dd = 3 v v max v inh , input high voltage 3.5 dv dd = 5 v v min 2.5 dv dd = 3 v v min xtal1 input capacitance 18 pf typ xtal2 output capacitance 18 pf typ rev. 0 ?6? ADUC836 specifications (continued) p arameter ADUC836 test conditions/comments unit logic outputs (not including xtal2) 2 v oh , output high voltage 2.4 v dd = 5 v, i source = 80 a v min 2.4 v dd = 3 v, i source = 20 a v min v ol , output low voltage 14 0.4 i sink = 8 ma, sclock, mosi/sdata v max 0.4 i sink = 10 ma, p1.0 and p1.1 v max 0.4 i sink = 1.6 ma, all other outputs v max floating state leakage current 2 ?0 a max floating state output capacitance 5 pf ty p power supply monitor (psm) av dd tr ip point selection range 2.63 four trip points selectable in this range v min 4.63 programmed via tpa1? in psmcon v max av dd power supply trip point accuracy ?.0 t max = 85? % max ?.0 t max = 125? % max dv dd tr ip point selection range 2.63 four trip points selectable in this range v min 4.63 programmed via tpd1? in psmcon v max dv dd power supply trip point accuracy ?.0 t max = 85 c % max ?.0 t max = 125 c % max wa tchdog timer (wdt) timeout period 0 nine timeout periods in this range ms min 2000 programmed via pre3? in wdcon ms max mcu core clock rate clock rate generated via on-chip pll mcu clock rate 2 98.3 programmable via cd2? bits in khz min pllcon sfr 12.58 mhz max start-up time at power-on 300 ms typ after external reset in normal mode 3 ms typ after wdt reset in normal mode 3 controlled via wdcon sfr ms typ from idle mode 10 s typ from power-down mode oscillator running osc_pd bit = 0 in pllcon sfr wake-up with int0 interrupt 20 s typ wake-up with spi interrupt 20 s typ wake-up with tic interrupt 20 s typ wake-up with external reset 3 ms typ oscillator powered down osc_pd bit = 1 in pllcon sfr wake-up with int0 interrupt 20 s typ wake-up with spi interrupt 20 s typ wake-up with external reset 5 ms typ flash/ee memory reliability characteristics 15 endurance 16 100,000 cycles min data retention 17 100 years min rev. 0 ADUC836 ?7? p arameter ADUC836 test conditions/comments unit power requirements dv dd and av dd can be set independently power supply voltages av dd , 3 v nominal operation 2.7 v min 3.6 v max av dd , 5 v nominal operation 4.75 v min 5.25 v max dv dd , 3 v nominal operation 2.7 v min 3.6 v max dv dd , 5 v nominal operation 4.75 v min 5.25 v max 5 v power consumption dv dd = 4.75 v to 5.25 v, av dd = 5.25 v power supply currents normal mode 18, 19 dv dd current 4 core clk = 1.57 mhz ma max dv dd current 13 core clk = 12.58 mhz ma typ 16 core clk = 12.58 mhz ma max av dd current 180 core clk = 1.57 mhz or 12.58 mhz a max power supply currents power-down mode 18, 19 core clk = 1.57 mhz or 12.58 mhz dv dd current 53 t max = 85?; osc. on, tic on a max 100 t max = 125?; osc. on, tic on a max dv dd current 30 t max = 85?; osc. off a max 80 t max = 125?; osc. off a max av dd current 1 t max = 85?; osc. on or osc. off a max 3 t max = 125?; osc. on or osc. off a max t ypical additional power supply currents core clk = 1.57 mhz (ai dd and di dd ) psm peripheral 50 a typ primary adc 1 ma typ auxiliary adc 500 a typ dac 150 a typ dual current sources 400 a typ 3 v power consumption dv dd = 2.7 v to 3.6 v power supply currents normal mode 18, 19 dv dd current 2.3 core clk = 1.57 mhz ma max dv dd current 8 core clk = 12.58 mhz ma typ 10 core clk = 12.58 mhz ma max av dd current 180 av dd = 5.25 v, core clk = 1.57 mhz or 12.58 mhz a max power supply currents power-down mode 18, 19 core clk = 1.57 mhz or 12.58 mhz dv dd current 20 t max = 85?; osc. on, tic on a max 40 t max = 125?; osc. on, tic on a max dv dd current 10 osc. off a typ av dd current 1 av dd = 5.25 v; t max = 85?; osc. on or osc. off a max 3 av dd = 5.25 v; t max = 125?; osc. on or osc. off a max rev. 0 ADUC836 ?8? notes 1 te mperature range for ADUC836bs (mqfp package) is ?0? to +125?. temperature range for ADUC836bcp (csp package) is ?0? to + 85?. 2 these numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 system zero-scale calibration can remove this error. 4 the primary adc is factory calibrated at 25? with av dd = dv dd = 5 v yielding this full-scale error of 10 v. if user power supply or temperature conditions are signi cantly different from these, an internal full-scale calibration will restore this error to 10 v. a system zero-scale and full-scale calibration will remove this error altogether. 5 gain error drift is a span drift. to calculate full-scale error drift, add the offset error drift to the gain error drift times the full-scale input. 6 the auxiliary adc is factory calibrated at 25? with av dd = dv dd = 5 v yielding this full-scale error of ?.5 lsb. a system zero-scale and full-scale calibration will remove this error altogether. 7 da c linearity and ac speci cations are calculated using: reduced code range of 48 to 4095, 0 to v ref ; reduced code range of 100 to 3950, 0 to v dd . 8 gain error is a measurement of the span error of the dac. 9 in general terms, the bipolar input voltage range to the primary adc is given by range adc = ?v ref 2 rn )/125, where: v ref = refin(+) to refin(? voltage and v ref = 1.25 v when internal adc v ref is selected. rn = decimal equivalent of rn2, rn1, rn0, e.g., v ref = 2.5 v and rn2, rn1, rn0 = 1, 1, 0 the range adc = ?.28 v. in unipolar mode, the effective range is 0 v to 1.28 v in our example. 10 1.25 v is used as the reference voltage to the auxiliary adc when internal v ref is selected via xref0 and xref1 bits in adc0con and adc1con, respectively. 11 in bipolar mode, the auxiliary adc can only be driven to a minimum of agnd ?30 mv as indicated by the auxiliary adc absolute a in voltage limits. the bipolar range is still ? ref to +v ref ; however, the negative voltage is limited to ?0 mv. 12 the ADUC836bcp (csp package) has been quali ed and tested with the base of the csp package oating. 13 pins con gured in spi mode, pins con gured as digital inputs during this test. 14 pins con gured in i 2 c mode only. 15 flash/ee memory reliability characteristics apply to both the flash/ee program memory and flash/ee data memory. 16 endurance is quali ed to 100 kcycles as per jedec std. 22 method a117 and measured at ?0?, +25?, +85?, and +125?. typical endurance at 25? is 700 kcycles. 17 retention lifetime equivalent at junction temperature (t j ) = 55? as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev will derate with junction temperature as shown in figure 16 in the flash/ee memory section. 18 po w er supply current consumption is measured in normal, idle, and power-down modes under the following conditions: normal mode: reset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, core executing internal software loop. idle mode: reset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, pcon.0 = 1, core executio n suspended in idle mode. power-down mode: reset = 0.4 v, all p0 pins and p1.2?1.7 pins = 0.4 v, all other digital i/o pins are open circuit, core cl k changed via cd bits in pllcon, pcon.1 = 1, core execution suspended in power-down mode, osc turned on or off via osc_pd bit (pllcon.7) in pllcon sfr. 19 dv dd power supply current will increase typically by 3 ma (3 v operation) and 10 ma (5 v operation) during a flash/ee memory progra m or erase cycle. speci cations subject to change without notice. rev. 0 ADUC836 ?9? ordering guide model temperature range package description package option ADUC836bs ?0? to +125? 52-lead plastic quad flatpack s-52 ADUC836bcp ?0? to +85? 56-lead chip scale package cp-56 eval-ADUC836qs quickstart development system absolute maximum ratings 1 (t a = 25?, unless otherwise noted.) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v a gnd to dgnd 2 . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? v to +5 v analog input voltage to agnd 3 . . . . . . ?.3 v to av dd + 0.3 v reference input voltage to agnd . . . . ?.3 v to av dd + 0.3 v ain/refin current (inde nite) . . . . . . . . . . . . . . . . . . 30 ma digital input voltage to dgnd . . . . . . ?.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . . . ?.3 v to dv dd + 0.3 v operating temperature range . . . . . . . . . . . . ?0? to +125? storage temperature range . . . . . . . . . . . . . . ?5? to +150? junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 150? ja thermal impedance (mqfp) . . . . . . . . . . . . . . . . . 90?/w ja thermal impedance (csp base floating) . . . . . . . . 52?/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215? infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220? notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 ag nd and dgnd are shorted internally on the ADUC836. 3 applies to p1.2 to p1.7 pins operating in analog or digital input modes. pin configurations 52-lead mqfp 1 13 14 26 40 52 27 39 ADUC836 top view (not to scale) pin 1 identifier 56-lead csp pin 1 identifier 1 14 15 28 29 42 43 56 ADUC836 top view (not to scale) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the ADUC836 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. rev. 0 ADUC836 ?10? pin function descriptions pin no. pin no. 52-lead 56-lead mqfp csp m nemonic type * description 1, 2 56, 1 p1.0/p1.1 i/o p1.0 and p1.1 can function as digital inputs or digital outputs and have a pull-up con guration as described for port 3. p1.0 and p1.1 have an increased current drive sink capability of 10 ma. p1.0/t2/pwm0 i/o p1.0 and p1.1 also have various sec ond ary functions as described below. p1.0 can be used to pro vide a clock input to timer 2. when enabled, counter 2 is incremented in response to a negative transition on the t2 input pin. if the pwm is enabled, the pwm0 output will appear at this pin. p1.1/t2ex/pwm1 i/o p1.1 can also be used to pro vide a con trol input to timer 2. when enabled, a pwm1 negative transition on the t2ex input pin will cause a timer 2 capture or reload event. if the pwm is enabled, the pwm1 output will appear at this pin. 3?, 2?, p1.2?1.7 i port 1.2 to port 1.7 have no dig i tal out put driver; they can func tion as a digital input 9?2 11?4 for which 0 must be written to the port bit. as a digital in put, these pins must be driven high or low externally. these pins also hav e the following analog functionality: p1.2/dac/iexc1 i/o the voltage out put from the dac or one or both current sources (200 ? or 2 200 ?) can be con g ured to ap pear at this pin. p1.3/ain5/iexc2 i/o auxiliary adc input or one or both current sources can be con g ured at this pin. pll with prog. clock divider watchdog timer 2304 bytes user ram power supply monitor ain3 ain4 ain5 ain1 ain2 refin refin iexc 2 iexc 1 ain mux temp sensor ain mux band gap reference v ref detect current source mux 200 a 200 a 5 av dd 6 agnd 20 21 dgnd 35 26 sclock 27 mosi/sdata 14 miso 13 ss xtal1 p0.0 (ad0) p0.1 (ad1) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) 43 44 45 46 49 50 51 52 p0.2 (ad2) buf ADUC836 auxiliary adc 16-bit - adc adc control and calibration pga primary adc 16-bit - adc adc control and calibration 3 22 t0 23 t1 2 t2ex t2 1 int0 int1 dac 40 ea 41 psen 17 txd 16 rxd 4 kbytes data flash/ee 62 kbytes program/ flash/ee uart serial port 8052 mcu core downloader debugger buf single-pin emulator spi/i 2 c serial interface 16-bit counter timers wake-up/ rtc timer xtal2 33 osc p1.0 (t2) p1.1 (t2ex) p1.2 (dac/iexc 1) p1.4 (ain1) p1.5 (ain2) p1.6 (ain3) p1.7 (ain4/dac) p1.3 (ain5/iexc 2) 1 2 3 4 9 10 11 12 p2.0 (a8/a16) p2.1 (a9/a17) p2.2 ( a10/a18) p2.3 (a11/a19) p2.4 ( a12/a20) p2.5 ( a13/a21) p2.6 ( a14/a22) p2.7 ( a15/a23) 28 29 30 31 36 39 38 37 16 p3.0 (rxd) 17 p3.1 (txd) 18 p3.2 ( int0 ) 19 p3.3 ( int1 ) 22 p3.4 (t0/pwmclk) 23 p3.5 (t1) 24 25 p3.7 ( rd ) p3.6 ( wr ) 12-bit voltage output dac 2 data pointers 11-bit stack pointer pwm0 pwm1 pwm control 1 2 32 42 ale 15 reset 48 dv dd 34 47 uart timer * pin numbers refer to the 52-lead mqfp package shaded areas represent the new features of the ADUC836 over the aduc816 dual 16-bit - dac dual 16-bit pwm mux dac control por 18 19 figure 1. detailed block diagram rev. 0 ADUC836 ?11? pin function descriptions (continued) pin no. pin no. 52-lead 56-lead mqfp csp mnemonic type * description p1.4/ain1 i primary adc, positive analog input p1.5/ain2 i primary adc, negative analog input p1.6/ain3 i auxiliary adc input or muxed primary adc, positive analog in put p1.7/ain4/dac i/o auxiliary adc input or muxed primary adc, neg a tive an a log input. the volt age output from the dac can also be con g ured to appear at this pin. 5 4, 5 av dd s an a log supply voltage, 3 v or 5 v 6 6, 7, 8 agnd s an a log ground. ground reference pin for the analog circuitry. 7 9 refin(? i reference input, negative terminal 8 10 refin(+) i reference input, positive terminal 13 15 ss i slave select input for the spi interface. a weak pull-up is present on this pin. 14 16 miso i/o master input/slave output for the spi interface. a weak pull-up is present on this input pin. 15 17 reset i reset input. a high level on this pin for 16 core clock cycles w hile the oscillator is ru nning resets the device. there is an internal weak pull-down and a schmitt trigger input stage on this pin. 16?9, 18?1, p3.0?3.7 i/o p3.0?3.7 are bidirectional port pins with internal pull-up resistors. po rt 3 pins that 22?5 24?7 have 1s written to them are pulled high by the internal pull- up resistors, and in that state can be used as inputs. as inputs, port 3 pin s being pulled externally low will source cur rent because of the internal pull-up resistors. when driv ing a 0-to-1 output transition, a strong pull-up is active for two cor e clock periods of the instruction cycle. port 3 pins also have various sec ond ary functions including: p3.0/rxd i/o receiver data for uart serial port p3.1/txd i/o transmitter data for uart serial port p3.2/ int0 i/o external interrupt 0. this pin can also be used as a gate control input to timer 0. p3.3/ int1 i/o external interrupt 1. this pin can also be used as a gate control input to timer 1. p3.4/t0/pwmclk i/o timer/counter 0 external input. if the pwm is enabled, an external clock may be input at this pin. p3.5/t1 i/o timer/counter 1 external input p3.6/ wr i/o external data memory write strobe. latches the data byte from port 0 into an external data mem o ry. p3.7/ rd i/o external data memory read strobe. enables the data from an ex ter nal data memory to port 0. 20, 34, 48 22, 36, 51, dv dd s digital supply, 3 v or 5 v 21, 35, 47 23, 37, 38, dgnd s digital ground. ground reference point for the digital circuitry. 50 26 sclock i/o serial interface clock for either the i 2 c or spi interface. as an input, this pin is a schmitt-triggered input, and a weak in ter nal pull-up is present on this pin unless it is outputting logic low. this pin can also be directly controlled in software as a digital output pin. 27 mosi/sdata i/o serial data i/o for the i 2 c interface or master output/slave input for the spi interface. a weak internal pull-up is present on this pin unless it is out put ting logic low. this pin can also be directly controlled in software as a digital out put pin. 28?1 30?3 p2.0?2.7 i/o port 2 is a bidirectional port with internal pull-up resistors. port 2 p ins that have 1s 36?9 39?2 (a8?15) writ ten to them are pulled high by the internal pull-up re sis tors, and in that state can (a16?23) be used as inputs. as inputs, port 2 pins being pulled ex ter nal ly low will source current because of the in ter nal pull-up resistors. po rt 2 emits the high order address bytes during f etch es from external program memory and middle and high order address bytes durin g accesses to the 24-bit external data memory space. 32 34 xtal1 i input to the crystal oscillator inverter 33 35 xt al2 o output from the crystal oscillator inverter. (see the hardware des ign con siderations section for description.) rev. 0 ADUC836 ?12? pin function descriptions (continued) pin no. pin no. 52-lead 56-lead mqfp csp mnemonic type * description 40 43 ea i/o external access en able, logic input. when held high, this input enables the de vice to fetch code from internal program memory locations 0000h to f7ffh. when held low, this input enables the device to fetch all in struc tions from ex ter nal program memory. to de ter mine the mode of code ex e cu tion, i.e., in ter nal or external, the ea pin is sampled at the end of an ex ter nal re set as ser tion or as part of a device power cycle. ea may also be used as an external emulation i/o pin, and therefore the voltage level at this pin must not be changed dur ing nor mal mode op er a tion as it may cause an emulation interrupt that will halt code execution. 41 44 psen o program store enable, logic output. this output is a control signal that enables the external program memory to the bus during external fetch op er a tions. it is active every six oscillator periods except dur ing ex ter nal data mem o ry accesses. this pin remains high during internal program ex e cu tion. psen can also be used to enable serial download mode when pulled low through a resistor at the end of an external reset assertion or as part of a device power cycle. 42 45 ale o address latch enable, logic output. this output is used to latc h the low byte (and page byte for 24-bit data address space accesses) of the address to external mem o ry during external code or data memory access cycles. it is activated every six oscillator periods except during an ex ter nal data mem o ry access. it can be disabled by setting the pcon.4 bit in the pcon sfr. 43?6 46?9 p0.0?0.7 i/o these pins are part of port 0, which is an 8-bit, open-drain, bi di rec tion al 49?2 52?5 (ad0?d3) i/o port. port 0 pins that have 1s written to them oat and in that state can be used (ad4?d7)a s high im ped ance inputs. an external pull-up resistor will be required on p0 outputs to force a valid logic high level ex ter nal ly. port 0 is also the mul ti plexed low order address and data bus dur ing ac cess es to external pro g ram or data mem o ry. in this application, it uses strong internal pull-ups when emitting 1s. * i = input, o = output, s = supply. rev. 0 ADUC836 ?13? memory organization the ADUC836 contains four different memory blocks: 62 kbytes of on-chip flash/ee program memory 4 kbytes of on-chip flash/ee data memory 256 bytes of general-purpose ram 2 kbytes of internal xram (1) flash/ee program memory the ad uc836 p rovides 62 kbytes of flash/ee program mem- o ry to run user code. the user can choose to run code from this internal memory or run code from an external pro g ram memory. if the user applies power or resets the device while the ea pin is pulled low externally, the part will execute code from the ex ter nal program space; otherwise, if ea is pulled high externally, the part defaults to code execution from its internal 62 kbytes of flash/ee program memory. unlike the aduc816, where code execution can over ow from the internal code space to external code space once the pc becomes g reater than 1fffh, the ADUC836 does not support the rollover from f7ffh in internal code space to f800h in external code space. instead, the 2048 bytes between f800h and ffffh will appear as nop instructions to user code. pe r manently embedded rm w are allows code to be serially down- loaded to the 62 kbytes of internal code space via the uart serial port while the device is in-circuit. no external hardware is required. 56 kbytes of the program memory can be reprogrammed dur ing r untime; thus the code space can be upgraded in the eld using a user de ned protocol or it can be used as a data mem o ry . this is discussed in more detail in the flash/ee memory section. (2) flash/ee data memory 4 kb ytes of flash/ee data memory are available to the user and can be accessed indirectly via a group of registers mapped into the special function register (sfr) area. access to the flash/ee data memory is discussed in detail in the flash/ee memory section. (3) general-purpose ram the general-purpose ram is divided into two separate mem o r ies: the upper and lower 128 bytes of ram. the lower 128 bytes of ram can be accessed through direct or indirect addressing; the upper 128 bytes of ram can only be accessed through indirect addressing as it shares the same address space as the sfr space, which can only be accessed through direct addressing. the lower 128 bytes of internal data memory are mapped as shown in figure 2. the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 through r7. the next 16 bytes (128 bits), locations 20h through 2fh above the register banks, form a block of directly addressable bit locations at bit addresses 00h through 7fh. the stack can be located anywhere in the inter- nal memory address space, and the stack depth can be expanded up to 2048 bytes. reset initializes the stack pointer to location 07h. any call or push pre-increments the sp before loading the stack. therefore, loading the stack starts from location 08h, which is also the rs t register (r0) of register bank 1. thus, if one is going to use more than one register bank, the stack pointer should be ini tial ized to an area of ram not used for data stor age. bit-addressable (bit addresses) four banks of eight registers r0?7 banks selected via bits in psw 11 10 01 00 07h 0fh 17h 1fh 2fh 7fh 00h 08h 10h 18h 20h reset value of stack pointer 30h general-purpose area figure 2. lower 128 bytes of internal data memory (4) internal xram the ADUC836 contains 2 kbytes of on-chip extended data mem- o ry . this memory, although on-chip, is accessed via the movx instruction. the 2 kbytes of internal xram are mapped into the bottom 2 kbytes of the external address space if the cfg836.0 bit is set. otherwise, access to the external data mem o ry will occur just like a standard 8051. even with the cfg836.0 bit set, access to the external xram will occur once the 24-bit dptr is greater than 0007ffh. external data memory space (24-bit address space) 000000h ffffffh cfg836.0 = 0 external data memory space (24-bit address space) 000000h ffffffh cfg836.0 = 1 0007ffh 000800h 2 kbytes on-chip xram figure 3. internal and external xram general notes pertaining to this data sheet 1. set im plies a logic 1 state and cleared implies a logic 0 state, unless otherwise stated. 2. set and cleared also imply that the bit is set or automatically cleared by the ADUC836 hardware, unless otherwise stated. 3. user software should not write 1s to reserved or unimplemented bits as they may be used in future products. 4. any pin numbers used throughout this data sheet refer to the 52-lead mqfp package, unless otherwise stated. rev. 0 ADUC836 ?14? when accessing the internal xram, the p0 and p2 port pins, as w ell as the rd and wr strobes, will not be output as per a stan- dard 8051 movx instruction. this allows the user to use these port pins as standard i/o. the upper 1792 bytes of the internal xram can be con gured to be used as an extended 11-bit stack pointer. by default, the stack will operate exactly like an 8052 in that it will roll over from ffh to 00h in the general-purpose ram. on the ADUC836 however, it is possible (by setting cfg836.7) to enable the 11-bit extended stack pointer. in this case, the stack will roll over from ffh in ram to 0100h in xram. the 11-bit stack pointer is visible in the sp and sph sfrs. the sp sfr is located at 81h as with a standard 8052. the sph sfr is lo cat ed at b7h. the 3 lsbs of this sfr contain the three extra bits nec es sary to ex tend the 8-bit stack point er into an 11-bit stack point er. upper 1792 bytes of on-chip xram (data + stack for exsp = 1, data only for exsp = 0) 256 bytes of on-chip data ram (data + stack) lower 256 bytes of on-chip xram (data only) 00h ffh 00h 07ffh cfg836.7 = 0 cfg836.7 = 1 100h figure 4. extended stack pointer operation external data memory (external xram) just like a standard 8051 compatible core, the ADUC836 can access external data memory using a movx instruction. the movx instruction automatically outputs the various control strobes required to access the data memory. the ADUC836, however, can access up to 16 mbytes of external data memory. this is an enhancement of the 64 kbytes external data memory space available on a standard 8051 compatible core. the external data memory is discussed in more detail in the ADUC836 hardware design considerations section. special function registers (sfrs) the sfr space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. it provides an interface between the cpu and all on-chip pe riph - er als. a block diagram showing the programming model of the ADUC836 via the sfr area is shown in figure 5. 128-byte special function register area 62 kbyte electrically reprogrammable nonvolatile flash/ee program memory 8051 compatible core other on-chip peripherals temp sensor current sources 12-bit dac serial i/o wdt, psm tic, pll dual - adcs 4 kbyte electrically reprogrammable nonvolatile flash/ee data memory 256 bytes ram 2k xram figure 5. programming model all registers, except the program counter (pc) and the four gen er al-purpose register banks, reside in the sfr area. the sfr registers include control, con guration, and data registers that provide an interface between the cpu and all on-chip pe riph er als. accumulator sfr (acc) a cc is the accumulator register, which is used for math op er a tions including addition, subtraction, integer multiplication, and division, and boolean bit ma nip u la tions. the mnemonics for accumulator-speci c instructions, refer to the accumulator as a. b sfr (b) the b register is used with the acc for multiplication and division operations. for other instructions, it can be treated as a general-purpose scratch pad register. data pointer (dptr) the data pointer is made up of three 8-bit registers, named dpp (page byte), dph (high byte), and dpl (low byte). these are used to provide memory addresses for internal and external code access and external data access. it may be manipulated as a 16-bit register (dptr = dph, dpl), although inc dptr instructions will automatically carry over to dpp, or as three independent 8-bit registers (dpp, dph, dpl). the ADUC836 supports dual data pointers. for more information, refer to the dual data pointer section. rev. 0 ADUC836 ?15? ta b le ii. pcon sfr bit designations bit name description 7 smod double uart baud rate 6 seripd spi power-down interrupt enable 5 int0pd int0 power-down interrupt enable 4 aleoff disable ale output 3 gf1 general-purpose flag bit 2 gf0 general-purpose flag bit 1 pd power-down mode enable 0 idl idle mode enable ADUC836 configuration sfr (cfg836) the cfg836 sfr contains the necessary bits to con gure the internal xram and the extended sp. by default it con g ures the user into 8051 mode, i.e., extended sp is disabled, internal xram is disabled. sfr address afh po w er-on default value 00h bit addressable no ta b le iii. cfg836 sfr bit designations bit name description 7 exsp extended sp enable. if this bit is set, the stack will roll over from sph/sp = 00ffh to 0100h. if this bit is clear, the sph sfr will be dis abled and the stack will roll over from sp = ffh to sp = 00h. 6 reserved for future use 5 reserved for future use 4 reserved for future use 3 reserved for future use 2 reserved for future use 1 reserved for future use 0 xramen xram enable bit. if this bit is set, the in- ter nal xram will be mapped into the lower 2 kbytes of the external address space. if this bit is clear, the inter nal xram will not be accessible and the external data memory will be mapped into the lower 2 kbytes of external data memory (see figure 3). stack pointer (sp and sph) the sp sfr is the stack pointer and is used to hold an internal ram address that is called the ?op of the stack. the sp reg is ter is incremented before data is stored, during push and call executions. while the stack ma y reside anywhere in on-chip ram, the sp register is initialized to 07h after a reset. this causes the stack to begin at location 08h. as mentioned earlier, the ADUC836 offers an extended 11-bit stack pointer. the t hree extra bits that make up the 11-bit stack point er are the 3 lsbs of the sph byte located at b7h. program status word (psw) the psw sfr contains several bits re ecting the current status of the cpu as detailed in table i. sfr address d0h po w er-on default value 00h bit addressable yes ta b le i. psw sfr bit designations bit name description 7 cy carry flag 6 ac auxiliary carry flag 5 f0 general-purpose flag 4 rs1 register bank select bits 3 rs0 rs1 rs0 selected bank 0 0 0 0 1 1 1 0 2 1 1 3 2 ov over ow flag 1 f1 general-purpose flag 0 p parity bit po w er control sfr (pcon) the pcon sfr contains bits for power saving options and general-purpose status ags, as shown in table ii. the tic (wake-up/rtc timer) can be used to accurately wake up the ADUC836 from power-down at regular intervals. to use the tic to wake up the ADUC836 from power-down, the osc_pd bit in the pllcon sfr must be clear and the tic must be enabled. sfr address 87h po w er-on default value 00h bit addressable no rev. 0 ADUC836 ?16? spicon f8h 04h reserved reserved reserved reserved reserved reserved not used reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used reserved reserved reserved reserved reserved dacl fbh 00h dach fch 00h daccon fdh 00h b f0h 00h i2ccon e8h 00h acc e0h 00h adcstat d8h 00h psw d0h 00h t2con 00h wdcon c0h 10h ip b8h 00h p3 b0h ffh ie a8h 00h p2 a0h ffh scon 98h 00h p1 90h ffh tcon 88h 00h p0 80h ffh adcmode d1h 00h econ b9h 00h ieip2 a9h a0h timecon a1h 00h sbuf 99h 00h tmod 89h 00h sp 81h 07h eah 55h of0m e2h 00h adc0m dah 00h adc0con d2h 07h rcap2l cah 00h chipid c2h 2 h hthsec a2h 00h tl0 8ah 00h dpl 82h 00h ebh 53h of0h e3h 80h adc0h dbh 00h adc1con d3h 00h rcap2h cbh 00h sec a3h 00h tl1 8bh 00h dph 83h 00h reserved reserved reserved reserved reserved gn1l ech 9ah of1l e4h 00h adc1l dch 00h sf d4h 45h tl2 cch 00h edata1 bch 00h min a4h 00h th0 8ch 00h dpp 84h 00h reserved gn1h edh 59h of1h e5h 80h adc1h ddh 00h icon d5h 00h th2 cdh 00h edata2 bdh 00h hour a5h 00h th1 8dh 00h reserved eadrl c6h 00h edata3 beh 00h intval a6h 00h spidat f7h 00h psmcon dfh deh pllcon d7h 03h edata4 bfh 00h pcon 87h 00h gn0m gn0h c8h pwmcon cfg836 dpcon sph pwm0l pwm0h pwm1l pwm1h b1h 00h b4h 00h b3h 00h b2h 00h b7h 00h afh 00h aeh 00h a7h 00h eadrh c7h 00h t3con 9eh 00h reserved reserved t3fd 9dh 00h reserved reserved reserved reserved reserved reserved reserved reserved 22 2 2 11 11 ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 eeh 0 edh 0 ech 0 i2cm ebh 0 eah e9h 0 e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits rdy0 dfh 0 rdy1 deh 0 cal ddh 0 noxref dch 0 err0 dbh 0 err1 dah d9h 0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rsi d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre2 c7h 0 pre1 c6h 0 pre0 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 wdwr c0h 0 bits bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah t1 99h 0 r1 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 1 0 0 0 0 0 0 0 pre3 000 0 11 mde mco mdi i2crs i2ctx i2ci ie0 89h 0 it0 88h 0 tcon 88h 00h bit mnemonic bit bit address mnemonic reset default value sfr address these bits are contained in this byte. reset default bit value sfr map key: sfr note: sfrs whose addresses end in 0h or 8h are bit addressable. notes 1 calibration coefficients are preconfigured at power-up to factory calibrated values. 2 these sfrs maintain their prereset values after a reset if timecon.0 = 1. reserved reserved reserved figure 6. special function register locations and their reset default values complete sfr map figure 6 shows a full sfr memory map and the sfr con- tents after reset. not used indicates unoccupied sfr locations. unoccupied locations in the sfr address space are not im ple ment ed, i.e., no register exists at this location. if an unoccupied location is read, an unspeci ed value is returned. sfr locations that are reserved for future use are shaded (re served) and should not be accessed by user software. rev. 0 ADUC836 ?17? adc sfr interface both adcs are controlled and con gured via a number of sfrs that are s ummarized here and described in more detail in the fol low ing sections. adcstat adc status register. holds general status of the primary and auxiliary adcs. adcmode adc mode register. controls general modes of operation for primary and auxiliary adcs adc0con primary adc control register. controls speci c con guration of primary adc. adc1con auxiliary adc control register. controls speci c con guration of auxiliary adc. sf sinc filter register. con g ures the dec ima tion f actor for the sinc 3 lter and thus the pri ma ry and aux il ia ry adc update rates. icon current source control register. al lows the user to control of the various on-chip cur rent source options. adc0m/h primary adc 16-bit con ver sion result is held in these two 8-bit registers. adc1l/h auxiliary adc 16-bit conversi on result is held in these two 8-bit registers. of0m/h primary adc 16-bit offset calibration coef cient is held in these two 8-bit reg is ters. of1l/h auxiliary adc 16-bit offset calibration coef cient is held in these two 8-bit reg is ters. gn0m/h primary adc 16-bit gain calibration coef cient is held in these two 8-bit reg is ters. gn1l/h auxiliary adc 16-bit gain calibration coef cient is held in these two 8-bit registers. adcstat (adc status register) this sfr re ects the status of both adcs including data ready, calibration, and various (adc related) error and warning conditions such as reference detect and conversion over o w/under ow ags. sfr address d8h po w er-on default value 00h bit addressable yes ta b le iv. adcstat sfr bit designations bit name description 7 rdy0 ready bit for primary adc. set by hardware on completion of adc conversion or calibration cy cle. cleared directly by the user or indirectly by writing to the mode bits to start another primary adc conver sion or calibration. the primary adc is in hib it ed from writing further results to its data or cal i bra tion registers until the rdy0 bit is cleared. 6 rdy1 ready bit for auxiliary adc. same de nition as rdy0 referred to the auxiliary adc. 5 cal calibration status bit. set by hardware on com ple tion of cal i bra tion. cleared indirectly by a write to the mode bits to start an oth er adc con ver sion or calibration. 4 noxref no ex ter nal reference bit (only active if primary or auxiliary adc is active) . set to indicate that one or both of the refin pins is oat ing or the applied voltage is below a speci ed threshold. when set, con ver sion results are clamped to all ones, if using external reference. cleared to indicate valid v ref . 3 err0 primary adc error bit. set by hardware to indicate that the result written to the primary adc data reg is ters has been clamped to all zeros or all ones. after a calibration, this bit also ags error con di tions that caused the calibration registers not to be writ ten. cleared by a write to the mode bits to initiate a con ver sion or cal i bra tion. 2 err1 auxiliary adc error bit. same de nition as err0 referred to the auxiliary adc. 1 reserved for future use 0 reserved for future use rev. 0 ADUC836 ?18? adcmode (adc mode register) used to control the operational mode of both adcs. sfr address d1h po w er-on default value 00h bit addressable no ta b le v. adcmode sfr bit designations bit name description 7 reserved for future use 6 reserved for future use 5 adc0en primary adc enable. set by the user to enable the primary adc and place it in the mode selected in md2?d0, below. cleared by the user to place the primary adc in power-down mode. 4 adc1en auxiliary adc enable. set by the user to enable the auxiliary adc and place it in the mode selected in md2?d0, below. cleared by the user to place the auxiliary adc in power-down mode. 3 reserved for future use 2 md2 primary and auxiliary adc mode bits. 1 md1 these bits select the operational mode of the enabled adc as follows: 0 md0 md2 md1 md0 0 0 0 adc power-down mode (power-on default) 0 0 1 idle mode. the adc lter and modulator are held in a reset state although the modulator clocks are still pro vid ed. 0 1 0 single conversion mode. a single con ver sion is performed on the enabled adc. on completion of the conversion, the adc data registers (adc0h/m and/or adc1h/l) are up dat ed, the relevant ags in the adcstat sfr are writ ten, and power-down is re-entered with the md2?d0 ac cord ing ly being written to 000. 0 1 1 con tin u ous conversion. the adc data registers are reg u lar ly updated at the selected update rate (see sf register). 1 0 0 internal zero-scale calibration. internal short automatically connected to the enabled adc input(s). 1 0 1 in ter nal full-scale calibration. internal or external v ref (as determined by xref0 and xref1 bits in adc0/1con) is automatically connected to the enabled adc input(s) for this cal i bra tion. 1 1 0 system zero-scale calibration. user should connect system zero-scale input to the enabled adc input(s) as selected by ch1/ch0 and ach1/ach0 bits in the adc0/1con register. 1 1 1 system full-scale calibration. user should connect system full-scale input to the enabled adc input(s) as selected by the ch1/ch0 and ach1/ach0 bits in the adc0/1con register. notes 1. any change to the md bits will immediately reset both adcs. a write to the md2? bits with no change is also treated as a res et. (see exception to this in note 3.) 2. if adc0con is written when adc0en = 1, or if adc0en is changed from 0 to 1, then both adcs are also immediately reset. in ot her words, the primary adc is gi v en priority over the auxiliary adc, and any change requested on the primary adc is immediately responded to. 3. on the other hand, if adc1con is written or if adc1en is changed from 0 to 1, only the auxiliary adc is reset. for example, i f the primary adc is con tin u ous ly converting when the auxiliary adc change or enable occurs, the primary adc continues undisturbed. rather than allow the auxiliary adc to o p er a te with a phase difference from the primary adc, the auxiliary adc will fall into step with the outputs of the pri ma ry adc. the result is that the rst con ver sion time for the auxiliary adc will be delayed up to three outputs while the auxiliary adc update rate is syn chro nized to the pri ma ry adc. 4. once adcmode has been written with a calibration mode, the rdy0/1 bits (adcstat) are im me di a te ly reset and the calibration commences. on com ple tion, the appropriate calibration registers are written, the relevant bits in adcstat are written, and the md2? bits are reset to 000 to indicate th e adc is back in power-down mode. 5. any calibration request of the auxiliary adc while the temperature sensor is selected will fail to complete. although the rd y1 bit will be set at the end of the calibration c ycle, no update of the calibration sfrs will take place and the err1 bit will be set. 6. calibrations are performed at maximum sf (see sf sfr) value, guaranteeing optimum calibration operation. rev. 0 ADUC836 ?19? adc0con (primary adc control register) and adc1con (auxiliary adc control register) the adc0con and adc1con sfrs are used to con gure the primary and auxiliary adc for reference and channel selection, unipolar or bipolar coding and, in the case of the primary adc, range (the auxiliary adc operates on a x ed input range of ? ref ). adc0con primary adc control sfr sfr address d2h po w er-on default value 07h bit addressable no adc1con auxiliary adc con trol sfr sfr ad dress d3h po w er-on default value 00h bit addressable no ta b le vi. adc0con sfr bit designations bit name description 7 reserved for future use 6 xref0 primary adc ex ter nal reference select bit. set by user to enable the primary adc to use the external reference via re fin(+)/refin(?. cleared by user to enable the primary adc to use the internal band gap ref er ence (v ref = 1.25 v). 5 ch1 primary adc chan nel selection bits. 4 ch0 written by the user to select the dif fer en tial input pairs used by the primary adc as follows: ch1 ch0 positive input negative input 0 0 ain1 ain2 0 1 ain3 ain4 1 0 ain2 ain2 (internal short) 1 1 ain3 ain2 3 uni0 primary adc un i po lar bit. set by user to enable unipolar coding, i.e., zero differential input will result in 000000h out put. cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000h out put. 2 rn2 primary adc range bits. 1 rn1 written by the user to select the primary adc input range as follows: 0 rn0 rn2 rn1 rn0 selected primary adc input range (v ref = 2.5 v) 0 0 0 ?0 mv (0 mv?0 mv in unipolar mode) 0 0 1 ?0 mv (0 mv?0 mv in unipolar mode) 0 1 0 ?0 mv (0 mv?0 mv in unipolar mode) 0 1 1 ?60 mv (0 mv?60 mv in unipolar mode) 1 0 0 ?20 mv (0 mv?20 mv in unipolar mode) 1 0 1 ?40 mv (0 mv?40 mv in unipolar mode) 1 1 0 ?.28 v (0 v?.28 v in unipolar mode) 1 1 1 ?.56 v (0 v?.56 v in unipolar mode) ta b le vii. adc1con sfr bit designations bit name description 7 reserved for future use 6 xref1 auxiliary adc ex ter nal reference bit. set by user to enable the auxiliary adc to use the external reference via refin(+)/refin(?. cleared by user to enable the auxiliary adc to use the internal band gap reference. 5 ach1 auxiliary adc chan nel selection bits. 4 ach0 written by the user to select the single-ended input pins used to drive the auxiliary adc as fol lows: a ch1 ach0 positive input negative input 0 0 ain3 agnd 0 1 ain4 agnd 1 0 temp sensor agnd (temp sensor routed to the adc input) 1 1 ain5 agnd 3 uni1 auxiliary adc un i po lar bit. set by user to enable unipolar coding, i.e., zero input will result in 0000h output. cleared by user to enable bipolar coding, i.e., zero input will result in 8000h output. 2 reserved for future use 1 reserved for future use 0 reserved for future use notes 1. when the temperature sensor is selected, user code must select internal reference via xref1 bit above and clear the uni1 bit (adc1con.3) to select bipolar coding. 2. the temperature sensor is factory calibrated to yield conversion results 8000h at 0?. 3. a +1? change in temperature will result in a +1 lsb change in the adc1h register adc conversion result. rev. 0 ADUC836 ?20? adc0h/adc0m (primary adc conversion result reg is ters) these two 8-bit registers hold the 16-bit conversion result from the primary adc. sfr address adc0h high data byte dbh adc0m middle data byte dah po w er-on default value 00h adc0h, adc0m bit addressable no adc0h, adc0m adc1h/adc1l (auxiliary adc conversion result registers) these two 8-bit registers hold the 16-bit conversion result from the auxiliary adc. sfr address adc1h high data byte ddh adc1l low data byte dch po w er-on default value 00h adc1h, adc1l bit addressable no adc1h, adc1l of0h/of0m (primary adc offset calibration registers * ) these two 8-bit registers hold the 16-bit offset calibration coef cient for the primary adc. these registers are con gured at pow er-on with a factory default value of 800000h. how ev er, these bytes will be au to mat i cal ly overwritten if an internal or sys tem zero-scale calibration of the primary adc is initiated by the user via md2? bits in the adcmode register. sfr address of0h primary adc offset coef cient high byte e3h of0m primary adc offset coef cient middle byte e2h po w er-on default value 80000h of0h, of0m respectively bit addressable no of0h, of0m of1h/of1l (auxiliary adc offset calibration registers * ) these two 8-bit registers hold the 16-bit offset calibration coef cient for the auxiliary adc. these registers are con g ured at pow er-on with a factory default value of 8000h. how ev er, these bytes will be au to mat i cal ly overwritten if an internal or system zero-scale cal i bra tion of the auxiliary adc is initiated by the user via the md2? bits in the adcmode register. sfr address of1h auxiliary adc offset coef cient high byte e5h of1l aux il ia ry adc offset co ef cient low byte e4h po w er-on default value 8000h of1h and of1l, respectively bit addressable no of1h, of1l gn0h/gn0m (primary adc gain calibration registers * ) these two 8-bit registers hold the 16-bit gain cal i bra tion coef cient for the primary adc. these registers are con g ured at pow er-on with a factory-calculated internal full-scale calibration coef cient. every device will have an individual coef cient. how ev er, these bytes will be au to mat i cal ly overwritten if an internal or sys tem full-scale calibration of the primary adc is initiated by the user via md2? bits in the adcmode register. sfr address gn0h primary adc gain coef cient high byte ebh gn0m pri ma ry adc gain coef cient middle byte eah po w er-on default value con g ured at factory final test; see notes above. bit addressable no gn0h, gn0m gn1h/gn1l (auxiliary adc gain calibration registers * ) these two 8-bit registers hold the 16-bit gain calibration coef cient for the auxiliary adc. these registers are con g ured at power-on with a factory-calculated internal full-scale cal i bra tion coef cient. every device will have an individual coef cient. however, these bytes will be au to mat i cal ly overwritten if an internal or system full-scale calibration of the auxiliary adc is initiated by the user via md2? bits in the adcmode register. sfr address gn1h auxiliary adc gain coef cient high byte edh gn1l auxiliary adc gain coef cient low byte ech po w er-on default value con g ured at factory final test; see notes above. bit addressable no gn1h, gn1l * these registers can be overwritten by user software only if mode bits md0? (adcmode sfr) are zero. rev. 0 ADUC836 ?21? sf (sinc filter register) the number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary adcs. this sfr cannot be written by user software while either adc is active. the update rate applies to both primary and auxiliary adcs and is calculated as follows: f sf f adc m o = 1 3 1 8 where: f adc = adc output up date rate f mod = modulator clock frequency = 32.768 khz sf = decimal value of sf register the allowable range for sf is 0dh to ffh. examples of sf v alues and cor re spond ing conversion update rates ( f adc ) and con- ve r sion times (t adc ) are shown in table viii. the pow er-on default v alue for the sf register is 45h, resulting in a default adc update rate of just under 20 hz. both adc inputs are chopped to mini- mize offset errors, which means that the settling time for a single conversion, or the time to a r st conversion result in continuous conversion mode, is 2 t adc . as men tioned earlier, all calibra- tion cycles will be carried out au to mat i cal ly with a max i mum, i.e., ffh, sf value to ensure op ti mum cal i bra tion per for mance. once a calibration cycle has com plet ed, the value in the sf register will be that programmed by user software. ta bl e viii. sf sfr bit designations sf(dec) sf(hex) f adc (hz) t adc (ms) 13 0d 105.3 9.52 69 45 19.79 50.34 255 ff 5.35 186.77 icon (current sources control register) the icon sfr is used to control and con gure the various excitation and burnout current source op tions available on-chip. sfr address d5h po w er-on default value 00h bit addressable no ta bl e ix. icon sfr bit designations bit name description 7 reserved for future use 6 bo burnout current enable bit. set by user to enable both transducer burnout current sources in the primary adc signal paths. cleared by the user to disable both transducer burnout current sources. 5 adc1ic auxiliary adc current correction bit. set by user to allow scaling of the auxiliary adc by an inter nal current source calibration word. 4 adc0ic primary adc current correction bit. set by user to allow scaling of the primary adc by an internal current source calibration word. 3 i2pin * current source-2 pin select bit. set by user to enable current source-2 (200 a) to external pin 3 (p1.2/dac/iexc1). cleared by user to enable current source-2 (200 a) to external pin 4 (p1.3/ain5/iexc2). 2 i1pin * current source-1 pin select bit. set by user to enable current source-1 (200 a) to external pin 4 (p1.3/ain5/iexc2). cleared by user to enable current source-1 (200 a) to external pin 3 (p1.2/dac/iexc1). 1 i2en current source-2 enable bit. set by user to turn on excitation current source-2 (200 a). cleared by user to turn off excitation current source-2 (200 a). 0 i1en current source-1 enable bit. set by user to turn on excitation current source-1 (200 a). cleared by user to turn off excitation current source-1 (200 a). * both current sources can be enabled to the same external pin, yielding a 400 a current source. rev. 0 ADUC836 ?22? primary and auxiliary adc noise performance t ables x, xi, and xii show the output rms noise in mv and output peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb) for some typical output update rates on both the pri ma ry and auxiliary adcs. the numbers are typical and are generated at a differential input voltage of 0 v. the output up date rate is selected via the sinc filter (sf) sfr. it is im por tant to note that the peak-to-peak resolution gures represent the resolution for which there will be no code icker within a six-sigma limit. the quickstart development system pc software comes com- plete with an adc noise evaluation tool. this tool can be easily used with the evaluation board to see these gures from silicon. ta bl e x. primary adc, typical output rms noise ( v) ty pical output rms noise vs. input range and update rate; output rms noise in v sf data update input range w ord rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 ta b le xi. primary adc, peak-to-peak resolution (bits) p eak-to-peak resolution vs. input range and update rate; peak-to-peak resolution in bits sf data update input range w ord rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13.5 14 15 16 16 16 16 16 255 5.35 14 15 16 16 16 16 16 16 ty pical rms resolution vs. input range and update rate: rms resolution in bits * sf data update input range w ord rate (hz) 20 mv 40 mv 80 mv 160 mv 320 mv 640 mv 1.28 v 2.56 v 13 105.3 14.7 15.7 16 16 16 16 16 16 69 19.79 16 16 16 16 16 16 16 16 255 5.35 16 16 16 16 16 16 16 16 * based on a six-sigma limit, the rms resolution is 2.7 bits greater than the peak-to-peak resolution. ta b le xii. auxiliary adc t ypical output rms noise vs. update rate * output rms noise in v sf data update input range w ord r a te (hz) 2.5 v 13 105.3 10.75 69 19.79 2.00 255 5.35 1.15 * adc converting in bipolar mode pe ak-to-peak resolution vs. update rate 1 p eak-to-peak res o lu tion in bits sf data update input range w ord rate (hz) 2.5 v 13 105.3 16 2 69 19.79 16 255 5.35 16 notes 1 adc converting in bipolar mode 2 in unipolar mode, peak-to-peak resolution at 105 hz is 15 bits. rev. 0 ADUC836 ?23? primary and auxiliary adc circuit description overview the ADUC836 incorporates two independent - adcs (primary and auxiliary) with on-chip digital ltering intended for the mea- surement of wide dynamic range, low fre quen cy signals such as those in weigh-scale, strain gage, pres sure transducer, or tempera- ture measurement applications. primary adc this adc is intended to convert the primary sensor input. the input is buffered and can be programmed for one of eight input ranges from ?0 mv to ?.56 v being driven from one of three differential input channel options ain1/2, ain3/4, or ain3/2. the input channel is internally buffered, allowing the part to handle signi cant source impedances on the analog input and allowing r/c ltering (for noise rejection or rfi reduction) to be placed on the analog inputs if required. on-chip burnout cur rents can also be turned on. these currents can be used to check that a transducer on the selected channel is still op er a tion al before a ttempting to take measurements. the adc employs a - conversion technique to realize up to 16 bits of no missing codes performance. the - modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. a sinc 3 programmable low-pass lter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 hz (186.77 ms) to 105.03 hz (9.52 ms). a chopping scheme is also employed to minimize adc offset errors. a block diagram of the primary adc is shown in figure 7. - modulator programmable digital filter - adc buffer agnd av dd refin(? refin(+) chop ain1 ain2 ain3 ain4 output average output scaling digtal output result written to adc0h/m/l sfrs pga chop output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor to null adc channel offset errors. - adc the - architecture ensures 24 bits no missing codes. the entire - adc is chopped to remove drift error. differential reference the external reference input to the ADUC836 is differential and facilitates ratiometric operation. the external reference voltage is selected via the xref0 bit in adc0con. reference detect circuitry tests for open or shorted reference inputs. analog input chopping the inputs are alternately reversed through the conversion cycle. chopping yields excellent adc offset and offset drift performance. burnout currents two 100na burnout currents allow the user to easily detect if a transducer has burned out or gone open-circuit. analog multiplexer a differential multiplexer allows selection of three fully differential pair options and additional internal short option (a in2?in2). the multiplexer is controlled via the channel selection bits in adc0con. buffer amplifier the buffer amplifier presents a high impedance input stage for the analog inputs, allowing significant external source impedances. the modulator provides a high frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. - modulator programmable digital filter the sinc 3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the sf sfr. the ouput word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. output scaling programmable gain amplifier the programmable gain amplifier allows eight unipolar and eight bipolar input ranges from 20mv to 2.56v (ext v ref = 2.5v). mux figure 7. primary adc block diagram rev. 0 ADUC836 ?24? the auxiliary adc has three external input pins (labeled ain3 to ain5) as well as an internal connection to the on-chip tem- perature sensor. all inputs to the auxiliary adc are single-ended inputs referenced to the agnd on the part. chan nel selection bits in the adc1con sfr detailed in table vii allow selection of one of four inputs. tw o input multiplexers switch the selected input channel to the on-chip buffer ampli er in the case of the primary adc and directly to the - modulator input in the case of the auxiliary adc. when the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the adc. mu x ain3 ain4 ain5 on-chip temperature sensor - modulator programmable digital filter - adc refin(? refin(+) chop output average output scaling digtal output result written to adc1h/l sfrs chop - adc the - architecture ensures 16 bits no missing codes. the entire - adc is chopped to remove drift errors. mux output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor to null adc channel offset errors. the modulator provides a high frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. - modulator programmable digital filter the sinc 3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the sf sfr. the ouput word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. output scaling analog input chopping the inputs are alternately reversed through the conversion cycle. chopping yields excellent adc offset and offset drift performance. differential reference the external reference input to the ADUC836 is differential and facilitates ratiometric operation. the external reference voltage is selected via the xref1 bit in adc1con. reference detect circuitry tests for open or shorted reference inputs. analog multiplexer a differential multiplexer allows selection of three external single ended inputs or the on-chip temp. sensor. the multiplexer is controlled via the channel selection bits in adc1con. figure 8. auxiliary adc block diagram auxiliary adc the auxiliary adc is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. this adc is not buffered and has a xe d input range of 0 v to 2.5 v (as sum ing an external 2.5 v reference). the single-ended inputs can be driven from ain3, ain4, or ain5 pins, or directly from the on-chip temperature sensor voltage. a block diagram of the aux il ia ry adc is shown in figure 8. analog input channels the primary adc has four associated analog input pins (labeled ain1 to ain4) that can be con gured as two fully dif fer en tial input channels. channel selection bits in the adc0con sfr detailed in table vi allow three combinations of differential pair selection as well as an additional shorted input option (ain2?in2). rev. 0 ADUC836 ?25? primary and auxiliary adc inputs the output of the primary adc multiplexer feeds into a high impedance input stage of the buffer ampli er. as a result, the primary adc inputs can handle signi cant source im ped anc es and are tailored for direct connection to external re sis tive-type sen- sors like strain gages or resistance tem per a ture detectors (rtds). the auxiliary adc, however, is unbuffered, resulting in higher analog input current on the auxiliary adc. it should be noted that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause dc gain errors depending on the output impedance of the source that is driving the adc inputs. analog input ranges the absolute input voltage range on the primary adc is restricted to between agnd + 100 mv to av dd ?100 mv. care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; oth er wise there will be a degradation in linearity performance. the absolute input voltage range on the auxiliary adc is restricted to between agnd ?30 mv to av dd + 30 mv. the slightly negative absolute input voltage limit does allow the possibility of monitor- ing small signal bipolar signals using the single-ended auxiliary adc front end. programmable gain ampli er the output from the buffer on the primary adc is applied to the input of the on-chip programmable gain ampli er (pga). the pga can be programmed through eight different unipolar input ranges and bipolar ranges. the pga gain range is pro g rammed via the range bits in the adc0con sfr. with the external reference select bit set in the adc0con sfr and an external 2.5 v reference, the unipolar ranges are 0 mv to 20 mv, 0 mv to 40 mv, 0 mv to 80 mv, 0 mv to 160 mv, 0 mv to 320 mv, 0 mv to 640 mv, 0 v to 1.28 v, and 0 to 2.56 v; the bipolar ranges are ?0 mv, ?0 mv, ?0 mv, ?60 mv, ?20 mv, ?40 mv, ?.28 v, and ?.56 v. these are the nom i nal ranges that should appear at the input to the on-chip pga. an adc range matching speci cation of 2 ? (typ) across all ranges means that calibration need only be car ri ed out at a single gain range and does not have to be repeated when the pga gain range is changed. t ypical matching across ranges is shown in figure 9. here, the primary adc is con gured in bipolar mode with an external 2.5 v reference, while just greater than 19 mv is forced on its in puts. the adc continuously converts the dc input voltage at an update rate of 5.35 hz, i.e., sf = ffh. in total, 800 con ver sion results are gathered. the r st 100 results are gathered with the primary adc operating in the ?0 mv range. the adc range is then switched to ?0 mv, 100 more con ver sion results are gathered, and so on, until the last group of 100 sam ples is gathered with the adc con- gured in the ?.56 v range. from figure 9, the variation in the sample mean through each range, i.e., the range matching, is seen to be of the order of 2 v. the auxiliary adc does not incorporate a pga and is con g ured for a x ed single input range of 0 to v ref . 0 100 200 300 400 500 600 700 800 sample count adc input voltage ?mv 19.372 19.371 19.370 19.369 19.368 19.367 19.366 19.365 19.364 adc range 20mv 40mv 80mv 320mv 2.56v 160mv 640mv 1.28v figure 9. primary adc range matching bipolar/unipolar inputs the analog inputs on the ADUC836 can accept either unipolar or bipolar input voltage ranges. bipolar input ranges do not imply that the part can handle negative voltages with respect to system a gnd. unipolar and bipolar signals on the ain(+) input on the pri ma ry adc are referenced to the voltage on the respective ain(? input. for example, if ain(? is 2.5 v and the primary adc is con gured for an analog input range of 0 mv to 20 mv, the input v oltage range on the ain(+) input is 2.5 v to 2.52 v. if ain(? is 2.5 v and the ADUC836 is con gured for an analog input range of 1.28 v, the analog input range on the ain(+) input is 1.22 v to 3.78 v (i.e., 2.5 v ?1.28 v). as mentioned earlier, the auxiliary adc input is a single-ended input with respect to the system agnd. in this context, a bi po lar signal on the auxiliary adc can only span 30 mv negative with respect to agnd before violating the voltage input limits for this adc. bipolar or unipolar options are chosen by programming the pri- mary and auxiliary unipolar enable bits in the adc0con and adc1con sfrs, respectively. this programs the relevant adc for either unipolar or bipolar operation. programming for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where cal i bra tions occur. when an adc is con gured for unipolar operation, the output coding is natural (straight) binary with a zero dif fer en tial input v oltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. when an adc is con gured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero dif- ferential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. rev. 0 ADUC836 ?26? reference input the ADUC836 |